1. Field of the Invention
The present invention relates to a line condition data collecting system for a telephone exchange and, more particularly, to a line condition data collecting system for the central processing unit (CPU) of an exchange.
2. Description of the Related Art
In a telephone exchange, the central processing unit (CPU) periodically collects line data to check on the origination of a call by a subscriber. This requires the CPU to consume a significant amount of time, resulting in deterioration of processing efficiency.
FIG. 1A is a block diagram of the system structure of a time division exchange. A subscriber line telephone set A is connected to a line concentrating and demultiplexing device 50 via a subscriber line and a subscriber circuit SLC. An up-highway UHW is formed by multiplexing the subscriber line with other subscriber lines in the line concentrating and demultiplexing device 50. A line processor (LPR) 51 watches the "off-hook" and "on-hook" conditions of each subscriber telephone set connected to the line concentrating and demultiplexing device 50 and generates line condition data corresponding to each subscriber.
The line condition data generated by the line processor (LPR) 51 is sent to the up-highway UHW after being multiplexed together with voice data in the line concentrating and demultiplexing device 50. Similar processing is performed in the LPR 51 and the line concentrating and demultiplexing device 60 which services subscriber B. The up-highways UHW are further multiplexed to a single line by multiplexing device MPX and then input to a network NW. As is well known, the network NW is composed of a primary time switch PTSW, a space switch and a secondary time switch. The voice data is sent through the network NW, while the line condition data generated by the line processors 51 and 61 is stored in a signal receiving memory RSM.
The central processing unit (CPU) 1 monitors the origination of a call by periodically reading the line condition data of each subscriber stored in the signal receiving memory RSM. The CPU 1 can also execute a command which instructs one of the line processors (LPR) 50 or 60 to send a ringing signal, etc., to the signal sending memory SSM.
A demultiplexing device DMPX executes an operation which is the reverse of that performed by the multiplexing device MPX and supplies the separated lines to down-highways DHW. Each separated down-highway DHW is further separated by the line concentrating and demultiplexing devices 50, 60 and is connected to the corresponding subscriber line and circuit SLC. The identified line processor LPR receives a command read from the signal sending memory SSM by the line concentrating and demultiplexing devices 50, 60 and executes the specified processing.
For example, the line processors (LPR) 51, 61 may each monitor eight (8) subscribers, so that one bit o an 8-bit word is assigned to each subscriber telephone set indicating "off-hook" as "1" and on-hook as "0". Therefore, as indicated in FIG. 1B, the RSM stores eight bits of data generated by the line processors (LPR) 51, 61 as one word. The command to the line processors (LPR) 51, 61 from the CPU 1 is also stored in the SSM in the same way.
The central processing unit CPU 1 accesses the signal receiving memory RSM through a slow speed bus (SP BUS) 4 and a signal receiving distributor (SRD) 3 to read the subscriber condition data stored in the signal receiving memory RSM. This process is described below with reference to FIGS. 2 and 3. FIG. 2 illustrates the connections between the CPU 1 of FIG. 1A and the network and FIG. 3 is a diagram for explaining the operation of FIG. 2.
As indicated in FIG. 3, at the beginning of a data transfer cycle, a central controller (CC) 11 in the CPU 1 transmits data to an output buffer 6 connected to a processor bus 7 (the internal bus of the CPU 1). WWhen data is stored in the output buffer 6, access of the SP BUS 4 connected to the SRD 3 starts. At the time of such access, data in the output buffer 6 is sent to the SP BUS 4 together with the signal SYNCS which indicates the effective period of data.
The data transmitted may be, for example, a readout command for line condition data stored in the signal receiving memory RSM, including the line processor (LPR) number corresponding to an address of 8-bit data (1 word). In this case, the SRD 3 prepares for return data (line condition data read from the RSM) produced in response to the raadout command. Thereafter, the SP BUS 4 changes to the data receiving mode from the sending mode with a predetermined timing controlled by an SP WINDOW signal. Thereby, the return data prepared by the SRD 3 is transmitted to the SP BUS 4 together with the signal SYNCW which indicates the effective period of data. The return data transmitted to the SP BUS 4 generates the input buffer timing signal from the SYNCW signal and stores the return data in the input buffer 5. The CPU 1 monitors the SYNCW signal, while waiting for the completion of data transfer, after transmission of the data to the output buffer 6. A single data transfer cycle terminates when the CPU 1 receives the data from the SP BUS 4.
As indicated in FIG. 3, a large part of one data transfer cycle is used for making access to the SP BUS 4 to read the line condition data from the network (NW) 2. This is due to the SP BUS 4 typically being a low speed bus, which is attributed to the following reasons.
Usually, the CPU 1 and the network (NW) 2 are installed in regions physically isolated from one another and the delay time caused by the length of the SP BUS 4 changes depending on the location of each element. Moreover, since many SRDs 3 are typically connected to the SP BUS 4 and a single CPU 1 typically controls multiple networks, the transfer time of data through an SP BUS 4 is not constant. Accordingly, transfer of data by the SP BUS 4 is carried out by an asynchronous transfer procedure using SYNCS, SYNCW and SW WINDOW. In this asynchronous transfer procedure, a time allowance is given for completing the procedure.
Therefore, the data transfer time through the SP BUS 4 is very long in comparison with the machine cycle of the CPU 1. Meanwhile, the CPU 1, as explained previously, monitors completion of the bus transfer cycle and waits for returning data. During this period, other processing may be carried out.